Serendipitous SEU hardening of resistive load SRAMs

Author

Koga, R. ; Kirshman, J.F. ; Pinkerton, S.D. ; Hansel, S.J. ; Crawford, K.B. ; Crain, W.R.

Author_Institution

Aerosp. Corp., Los Angeles, CA, USA

fYear

1995

fDate

18-22 Sep 1995

Firstpage

354

Lastpage

358

Abstract

High and low resistive load versions of Micron Technology´s MT5C1008C(128 K×8) and MT5C2561C(256 K×1) SRAMs were tested for SEU vulnerability. Contrary to computer simulation results, SEU susceptibility decreased with increasing resistive load A substantially larger number of multiple-bit errors were observed for the low resistive load SRAMs, which also exhibited a “1”→“0” to “0”→“1” bit error ratio close to unity; in contrast, the high resistive load devices displayed a pronounced error bit polarity effect. Two distinct upset mechanisms are proposed to account for these observations

Keywords

CMOS memory circuits; SRAM chips; errors; ion beam effects; radiation hardening (electronics); 1024 Kbit; 256 Kbit; MT5C1008C; MT5C2561C; Micron Technology; SEU hardening; SEU susceptibility; SEU vulnerability testing; bit error ratio; error bit polarity effect; high resistive load devices; low resistive load devices; multiple-bit errors; resistive load SRAMs; upset mechanisms; Aerospace testing; CMOS technology; Circuits; Computer errors; Computer simulation; MOSFETs; Particle beams; Random access memory; SRAM chips; Single event upset;

fLanguage

English

Publisher

ieee

Conference_Titel

Radiation and its Effects on Components and Systems, 1995. RADECS 95., Third European Conference on

Conference_Location

Arcachon

Print_ISBN

0-7803-3093-5

Type

conf

DOI

10.1109/RADECS.1995.509802

Filename

509802