Title :
Performance bounds for distributed memory multithreaded architectures
Author :
Zuberek, W.M. ; Govindarajan, R.
Author_Institution :
Dept. of Comput. Sci., Memorial Univ. of Newfoundland, St. John´´s, Nfld., Canada
Abstract :
In distributed memory multithreaded systems, the long memory latencies and unpredictable synchronization delays are tolerated by context switching, i.e., by suspending the current thread and switching the processor to another thread waiting for execution. Simple analytical upper bounds on performance measures are derived using throughput analysis and extreme values of some model parameters. These derived bounds are compared with performance results obtained by simulation of a detailed model of the analyzed architecture.
Keywords :
distributed memory systems; multi-threading; parallel architectures; performance evaluation; analytical upper bounds; context switching; distributed memory multithreaded architectures; distributed memory multithreaded systems; memory latencies; performance bounds; performance measures; synchronization delays; throughput analysis; Memory architecture; Multithreading; Network topology; Performance analysis; Process design; Steady-state; Supercomputers; Switches; Throughput; Yarn;
Conference_Titel :
Systems, Man, and Cybernetics, 1998. 1998 IEEE International Conference on
Print_ISBN :
0-7803-4778-1
DOI :
10.1109/ICSMC.1998.725414
