Title :
Design of a time-slot-interchanger and other TDM bus interfacing issues
Author_Institution :
Cyclades Corp., Fremont, CA, USA
Abstract :
This paper shows the design for an inexpensive time-slot-interchanger (TSI) for interchanging time-slot data between several time-division-multiplexed (TDM) busses. Additionally, many TDM bus-interfacing problems are discussed and solutions presented. The example TSI, design interfaces eight T1/E1 lines, although it is expandable in both the number of lines and speed. Routing of time-slot-data is done through a routing table stored in SRAM. It allows the data from one time slot to be routed to another time-slot on the same or different TDM bus. The TSI also has features that allow for the control of external buffers and non-TDM capable chips. It also allows for the generation of auxiliary frame sync signals for those difficult to interface chips. The TSI logic can be implemented in a <10K gate FPGA and small external Sync-SRAM- for a very low cost solution
Keywords :
SRAM chips; buffer storage; field programmable gate arrays; file organisation; system buses; telecommunication network routing; time division multiplexing; 10 kbit; TDM bus interfacing; TDM bus-interfacing; VHDL; external buffers; routing; routing table; time-division-multiplexed busses; time-slot-data; time-slot-interchanger; Clocks; Costs; Field programmable gate arrays; Logic; Random access memory; Routing; Signal generators; Switches; Time division multiplexing; Very high speed integrated circuits;
Conference_Titel :
Aerospace Conference, 1998 IEEE
Conference_Location :
Snowmass at Aspen, CO
Print_ISBN :
0-7803-4311-5
DOI :
10.1109/AERO.1998.682218
