DocumentCode
2201333
Title
A fast tagged sorter used in 100/10 Mbps routers
Author
Chua-Chin Wang ; Hsin-Long Wu ; Shao-Ku Huang
Author_Institution
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
fYear
2000
fDate
13-15 June 2000
Firstpage
376
Lastpage
377
Abstract
This paper presents a very fast circuit for a tagged sorter which has been integrated in 100/10 Mbps routers to resolve the re-ordering problem of incoming packets. The utilization of both edges of the clock is presented, which can drastically improve the clock speed and the throughput.
Keywords
packet switching; telecommunication network routing; 10 Mbit/s; 100 Mbit/s; clock edges; clock speed; fast tagged sorter; packet re-ordering problem resolution; performance simulations; routers; throughput; very fast circuit; Boundary conditions; Circuits; Clocks; Councils; H infinity control; Hardware; Mobile handsets; Sorting; Switches; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics, 2000. ICCE. 2000 Digest of Technical Papers. International Conference on
Conference_Location
Los Angles, CA, USA
Print_ISBN
0-7803-6301-9
Type
conf
DOI
10.1109/ICCE.2000.854693
Filename
854693
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