Modeling and analysis using Petri nets for semiconductor fabrication

A class of extended Petri nets is proposed for modeling semiconductor fabrication systems, where it is assumed that wafers are stored in the same buffer when they are waiting for either rework or a subsequent operation. An extended net is synthesized by merging net modules that are especially useful for semiconductor fabrication. For qualitative analysis, the synthesized extended net is first reduced to an ordinary net. It is shown that the reduced net is bounded. The reduced net is proven to be live and almost reversible if and only if there are no empty siphons. Almost reversibility is slightly weaker than reversibility in-that the former guarantees all in-process parts can be completed but the system may not be reset in terms of periodic maintenance. Using Chu and Xie´s (1997) mixed integer programming approach, the existence of empty siphons can efficiently be checked.