Title :
Analysis of SEU effects in a pipelined processor
Author :
Rebaudengo, M. ; Reorda, M. Sonza ; Violante, M.
Author_Institution :
Dipt. di Automatica e Informatica, Politecnico di Torino, Italy
Abstract :
Modern processors embed features such as pipelined execution units and cache memories that can hardly be controlled by programmers through the processor instruction set. As a result, software-based fault injection approaches are no longer suitable for assessing the effects of SEUs in modern processors, since they are not able to evaluate the effects of SEUs affecting pipelines and caches. In this paper we report an analysis of a commercial processor core where the effects of SEUs located in the processor pipeline and cache memories are studied. Moreover the obtained results are compared with those software-based approaches provide. Experimental results show that software-based approaches may lead to errors during the failure rate estimation of up to 400%.
Keywords :
cache storage; fault simulation; fault tolerant computing; field programmable gate arrays; hardware description languages; multiprocessing systems; pipeline processing; radiation hardening (electronics); software tools; FPGA-based environment; SEU effects; SPARC; VHDL code; cache memories; failure rate estimation; fault injection environment; fault tolerance; high-performance processors; matrix multiplication program; pipelined processor; processor core; processor-hidden parts; software tool; software-based approaches; transient bit-flip; Application software; Automatic control; Cache memory; Circuit faults; Costs; Error analysis; Pipelines; Programming profession; Registers; Safety;
Conference_Titel :
On-Line Testing Workshop, 2002. Proceedings of the Eighth IEEE International
Print_ISBN :
0-7695-1641-6
DOI :
10.1109/OLT.2002.1030193
