DocumentCode
2203118
Title
Recovering sequential circuits from temporary faults: the survival capability of scan-cells
Author
Santos, Jose Miguel Vieira dos
fYear
2002
fDate
2002
Firstpage
179
Abstract
The recovery technique introduced in this paper can be implemented in new designs and may allow sequential circuits to recover from many temporary faults. It is assumed that errors will be detected by other means. The memory elements of the mission circuit are implemented with standard, slightly enhanced, scan-cells that work as stand-alone, needing no external control or support.
Keywords
boundary scan testing; logic testing; sequential circuits; combinatorial logic; dependability; scan-based techniques; scan-cells; sequential circuits recovery; survival capability; temporary faults; Application specific integrated circuits; Binary search trees; Built-in self-test; Circuit faults; Circuit testing; Latches; Logic testing; Reconfigurable logic; Robotics and automation; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Workshop, 2002. Proceedings of the Eighth IEEE International
Print_ISBN
0-7695-1641-6
Type
conf
DOI
10.1109/OLT.2002.1030205
Filename
1030205
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