Current Pumping and Voltage Pulling to Maximize Speed: An Application to a 2.5 Gsps Flash ADC in 350 nm Standard CMOS Process

As process technologies slow down in their miniaturization, system design relies more heavily on innovation rather than technology to push the limits of speed beyond that of the existing systems. Parasitic capacitances dominate the paths in which the signals traverse through the circuit and the speed of operation largely depends on the reduction of these parasitics and on how fast these parasitics could be charged or discharged. This paper presents an innovation in this regime. Two innovative techniques, current pumping and voltage pulling are shown and their application to the sample and hold, pre-amplifier and latch components of a Flash Analog-to-Digital converter (ADC) is provided; It is shown that the frequency of operation can be pushed to double the initial, to 2.5 Gsps in 0.35 um CMOS technology.