DocumentCode
2203424
Title
Injecting multiple upsets in a SEU tolerant 8051 micro-controller
Author
Lima, F. ; Carro, L. ; Velazco, R. ; Reis, R.
Author_Institution
Fed. Univ. of Rio Grande do Sul, Brazil
fYear
2002
fDate
2002
Firstpage
194
Abstract
This paper investigates the behavior of a SEU tolerant 8051-like micro-controller protected by single error correction Hamming code in the presence of multiple upsets. Upsets were randomly injected in all sensitive parts of the design. The experiment was emulated in a Virtex FPGA platform. Results evaluate the robustness of the tolerant 8051 in a multiple upsets environment.
Keywords
Hamming codes; circuit CAD; error correction codes; field programmable gate arrays; integrated circuit testing; microcontrollers; radiation hardening (electronics); SEU tolerant 8051 microcontroller; Virtex FPGA; memory refreshing; multiple upsets; multiple upsets injection; randomly injected upsets; robustness; single bit upsets; single error correction Hamming code; Clocks; Error correction codes; Field programmable gate arrays; Flip-flops; Laboratories; Microcontrollers; Protection; Registers; Robustness; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Workshop, 2002. Proceedings of the Eighth IEEE International
Print_ISBN
0-7695-1641-6
Type
conf
DOI
10.1109/OLT.2002.1030217
Filename
1030217
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