DocumentCode :
2203650
Title :
Hardware system design of SD card reader and image processor on FPGA
Author :
Yang, Yansi ; Yang, Yingyun ; Niu, Lipi ; Wang, Huabin ; Liu, Bo
Author_Institution :
Inf. Eng. Sch., Commun. Univ. of China, Beijing, China
fYear :
2011
fDate :
6-8 June 2011
Firstpage :
577
Lastpage :
580
Abstract :
We designed a useful digital signal generating system which transforms various file data stored in SD card into SDI output signal based on the FPGA hardware platform. This paper presents the hardware design and implementation of the system, which includes two steps. First step is the design of the NIOS II system, which includes SRAM controller and SD card controller IP core design. Second step is the generation of the whole functional SOPC system which using Quartus II development tool. NIOS II system is integrated with the scrambling encoders in this step. And then the hardware system is implemented.
Keywords :
SRAM chips; field programmable gate arrays; flash memories; image processing; integrated circuit design; FPGA hardware platform; NIOS II system; Quartus II development tool; SD card controller IP core design; SD card reader; SDI output signal; SOPC system; SRAM controller; digital signal generating system; file data; hardware system design; image processor; scrambling encoder; Automation; Conferences; FPGA; NIOS II CPU; SD card; SDI signal; SOPC;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Information and Automation (ICIA), 2011 IEEE International Conference on
Conference_Location :
Shenzhen
Print_ISBN :
978-1-4577-0268-6
Electronic_ISBN :
978-1-4577-0269-3
Type :
conf
DOI :
10.1109/ICINFA.2011.5949060
Filename :
5949060
Link To Document :
بازگشت