The Implementation and Analysis of a New Self-sampling P1 Control All Digital Phase-locked Loop

A self-sampling PI (proportional-integral) control all digital phase-locked loop (ADPLL) is introduced in this paper. Our design is based on the self-sampling PI control scheme. An advantage of this is that the transfer function as linear approximation of the system model remains almost the same at different lock point, a feature enabling theoretical analysis and systematic design. The complete design procedure developed with field programmable gate array (FPGA) devices and the detailed theoretical analyses are presented. Static, dynamic results of simulation and experiments are also presented, which show and verify that this ADPLL has good behaviors over wide tracking speed, excellent stability and flexible control characteristics. The ADPLL can act as a key part or a key module in a system on chip (SoC) digital system to simply the entire system´s hardware architecture and ensure the high system reliability