Title :
FPGA-Based High Area Efficient Time-To-Digital IP Design
Author :
Lin, Min-Chuan ; Tsai, Guo-Ruey ; Liu, Chun-Yi ; Chu, Shi-Shien
Author_Institution :
Dept. of Electron. Eng., Kun-Shan Univ.
Abstract :
This paper proposes a novel design for a highly area efficient FPGA-based TDC (time to digital converter) IP (intelligent property) with resolution less than 30 ps. To avoid the unpredictable internal place and route (P&R) delay, a modified ring oscillator is presented. By integrating the gates delay and P&R delay, a design by combining schematic and VHDL codes, can generate a predictable and stable TDC module built in a Xilinx FPGA
Keywords :
analogue-digital conversion; delays; field programmable gate arrays; hardware description languages; oscillators; P&R delay; VHDL codes; Xilinx FPGA; intelligent property design; logic gate delay; ring oscillator; time-to-digital converter; Clocks; Delay effects; Delay lines; Field programmable gate arrays; Frequency; Hardware; Phase measurement; Pulse measurements; Ring oscillators; Time measurement;
Conference_Titel :
TENCON 2006. 2006 IEEE Region 10 Conference
Conference_Location :
Hong Kong
Print_ISBN :
1-4244-0548-3
Electronic_ISBN :
1-4244-0549-1
DOI :
10.1109/TENCON.2006.343706
