Circuit, MOSFET, and front end process integration trends and challenges for the 180 nm and below technology generations: an International Technology Roadmap for Semiconductors perspective

The IC industry is continuing to follow Moore´s Law (Moore, 1995) by rapidly scaling CMOS technology into the deep submicron regime, resulting in increased chip speed, decreased power dissipation per function, increased transistor and function density, and lower cost per function. However, this rapid scaling results in major problems and issues, including maintaining simultaneously large MOSFET drive current and low MOSFET source/drain (S/D) leakage currents, controlling the gate leakage for very thin gate oxides, fabrication and control of very abrupt, shallow S/D functions, etc. These issues are becoming more difficult to handle with succeeding technology generations. In this paper, the key circuit, MOSFET device, and front-end process integration scaling issues and potential solutions are discussed from an International Technology Roadmap for Semiconductors (1999) perspective