Yield enhancement for deep-submicron CMOS process by optimizing gate poly dimension

Gate poly dimension control is one of the most critical processing conditions to device yield, because it directly determines the transistor characteristics. For a particular deep submicron CMOS analog product, it is identified that low gate poly dimension is leading to poor yield performance. Much engineering work has been designed and carried out to study the various factors that affect gate poly feature size. These factors include lithographic masking condition, poly dry etch bias, within-wafer and wafer-to-wafer non-uniformity. It is found, that the worst case combination of all these factors could create a 0.23 μm gate poly, which drawn width is 0.35 μm. A focus-energy-matrix experiment was performed. The correlation between gate poly processing conditions and the device performance, as well as product yield, has been established