Defect Engineering and Stress Control in Advanced Devices on High-Mobility Substrates

The downscaling of CMOS below 45 nm has triggered the use of high-mobility substrates in order to compensate the mobility degradation related to the implementation of high-k dielectrics. Strain engineering has become a very popular technique to boost up the mobility and drive current. This paper discusses the electrical performance of junctions and transistors processed in strained Si on thin (250-350 nm) strain relaxed SiGe buffer (SRB) layers. The impact of the substrate (misfit and threading dislocation density, use of a C-rich layer in the SiGe buffer, global or locally epitaxial layer) and processing parameters (anneal conditions and doping type) on a variety of performance parameters such as transconductance, mobility, diode leakage current, minority carrier lifetime and low frequency noise are investigated. Some physical models are proposed to explain the experimental observations. Finally, the potential and issues with alternative high-mobility substrates will be briefly highlighted