Integration of RTL and precedence graphs with a static scheduler as verifier

We present an approach to specification and verification of distributed hard real-time systems. By integrating RTL and precedence constraints, we combine the comprehensiveness of precedence graphs with the expressive power and proofability of RTL. Thus, our approach allows easy comprehension by the human designer and formal correctness. We propose to use a static scheduling algorithm based on heuristic search to carry out a constructive proof of the set of formulas resulting form a design combining both methods. As the precedence structure is kept, the number of formulae checked at each search point is drastically reduced. Furthermore, we extend RTL to be applicable to distributed systems with preemptable tasks