High-level synthesis for testability

Progress in synthesis development has made commercially available tools that allow automatic synthesis of designs, starting from their RTL description. More recently, some tools even starting from the behavioral description have appeared on the market. However, the synthesized designs an rather hard to test. What is commonly achieved is to add testability features at the gate level, after the synthesis process has been done, which results in high area overhead and poor design performances. A lot of research work is currently on-going trying to take into account testability features at higher levels, that is, RTL or even behavioral level. We propose a general framework for an efficient high-level synthesis or testability methodology