Design and implementation of asynchronous parallel multiply-accumulate arithmetic architectures

In this paper, the conventional modified-Booth and Baugh-Wooley array multiplication algorithms are exploited and applied to the design and ASIC implementation of asynchronous parallel multiply-accumulate arithmetic architectures. Gate-level parameterization of the resulting multiply-accumulate arithmetic architectures is achieved in terms of the constituent multiplier, multiplicand, and addend wordlengths. This is subsequently used to quantify the performance characteristics of the arithmetic architectures in terms of the required chip area and the achievable throughput. It is shown that high-performance characteristics can be achieved, (a) by encoding the intermediate partial-product sums in the modified-Booth multiplication by using signed-binary representation, and by (b) asynchronous least significant word sign determination and signed binary to two´s complement conversion