Title :
Buffer size optimization for full-search block matching algorithms
Author :
Yeh, Yuan-Hau ; Lee, Chen-Yi
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
This paper presents how to find optimized buffer size for VLSI architectures of full-search block matching algorithms. Starting from the DG (dependency graph) analysis, we focus in the problem of reducing the internal buffer size under minimal I/O bandwidth constraint. As a result, a systematic design procedure for buffer optimization is derived to reduce realization cost
Keywords :
VLSI; computer vision; image processing; motion estimation; I/O bandwidth constraint; VLSI architectures; buffer size optimization; dependency graph analysis; full-search block matching algorithms; internal buffer size; optimized buffer size; systematic design procedure; Algorithm design and analysis; Bandwidth; Computer architecture; Cost function; Design optimization; Focusing; Hardware; Pattern matching; Very large scale integration; Video compression;
Conference_Titel :
Application-Specific Systems, Architectures and Processors, 1997. Proceedings., IEEE International Conference on
Conference_Location :
Zurich
Print_ISBN :
0-8186-7959-X
DOI :
10.1109/ASAP.1997.606814
