Cu barrier/seed technology development for sub-0.10 micron copper chips

Author

Ding, Peijun ; Chen, Ling ; Fu, Jianming ; Chin, Barry ; Mosely, Rod ; Xu, Zheng ; Yao, Gongda

Author_Institution

Appl. Mater. Inc, Santa Clara, CA, USA

Volume

1

fYear

2001

fDate

2001

Firstpage

405

Abstract

Advanced PVD technologies have been reviewed for copper barrier-seed applications for different device nodes. Each new device generation requires improved step coverage and reduced overhang. With each shift in deposition technology, there have been process and hardware advancements to meet decreasing feature sizes and increasing aspect ratios. The extension of PVD to 0.1 μm has delayed the need for a CVD barrier and seed solution. However, PVD´s limitations in step coverage, and the introduction of porous low-k dielectrics may necessitate a transition to CVD barriers below 0.10 μm. The process integration of SIP-Cu and a proven barrier solution TDMAT (tetrakis dimethyl amino titanium)-based CVD TiSiN is also discussed in this paper

Keywords

CVD coatings; copper; diffusion barriers; integrated circuit interconnections; integrated circuit metallisation; nanotechnology; sputtered coatings; 0.10 micron; CVD TiSiN; Cu; Cu barrier/seed technology development; PVD; TDMAT; aspect ratios; deposition technology; porous low-k dielectrics; reduced overhang; step coverage; sub-0.10 micron Cu chips; tetrakis dimethyl amino titanium; Argon; Atherosclerosis; Atomic layer deposition; Copper; Dielectrics; Hardware; Metallization; Plasma sources; Radio frequency; Sputtering;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6520-8

Type

conf

DOI

10.1109/ICSICT.2001.981505

Filename

981505