The impact of changes in the backend deposition technologies on wafer cleaning for sub 130 nm devices

In the present paper an overview is given over the impact that the changing backend deposition technologies have on stripping / cleaning and the photoresist development area. Three areas will be discussed with great detail: (a) Dielectric deposition, (b) metallization, and (c) lithography. As device nodes keep shrinking and, concurrently, the speed of semiconductor devices increases, new dielectric and conductor materials were needed, and have been introduced. This had, and will have, a tremendous impact on the way wafers are being stripped and cleaned. Conventional technologies, such ashing and wet clean, might no longer be applicable for certain applications. At the same time, in the lithography area, pattern collapse, in particular at around the 100 nm technology node, will become a big issue. In the present paper all of the above issues are addressed and potential solutions are offered