Backside films and charging during via etch in LOCOS and STI technologies

Author

Hook, Terence B.

Author_Institution

IBM Microelectron. Div., Essex Junction, VT, USA

fYear

1998

fDate

4-5 Jun 1998

Firstpage

11

Lastpage

14

Abstract

Films on the back of wafers affect charging during via etch for two CMOS technologies. One technology is LOCOS-based (local oxidation of silicon), with the backside conductive during critical process steps. The other is STI-based (shallow trench isolation), with the backside insulated during key steps. The conductive backside causes charging damage during via etch, as evidenced by threshold voltage shifts and the increased hot-electron sensitivity of monitoring devices. Data from large and small vias indicate that the electron-shading mechanism of charging damage is responsible for the effect

Keywords

CMOS integrated circuits; hot carriers; integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; integrated circuit yield; isolation technology; oxidation; plasma materials processing; sensitivity; sputter etching; CMOS technology; LOCOS technology; STI technology; Si; SiO₂-Si; charging damage; conductive backside charging damage; conductive wafer backside; critical process steps; electron-shading mechanism; hot-electron sensitivity; insulated wafer backside; local oxidation of silicon; monitoring devices; shallow trench isolation; threshold voltage shift; via etch; via size; wafer backside film charging effects; wafer backside films; CMOS technology; Chemical technology; Conductivity; Etching; Insulation; Isolation technology; Oxidation; Silicon on insulator technology; Substrates; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Plasma Process-Induced Damage, 1998 3rd International Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

0-9651577-2-5

Type

conf

DOI

10.1109/PPID.1998.725562

Filename

725562