Title :
Gate Layout Improvement Aimed at Testability
Author :
Blyzniuk, Mykola
Author_Institution :
Ivan Franko Nat. Univ. of L´´viv
Abstract :
In the presented paper the improvement of the layout of complex standard gates from the industrial cell library aimed at decreasing the probability of occurrence of undetectable faults is considered. Such improvement allows us to determine the defect coverage table correctly and as a result to estimate properly the optimal sequence of input test pattern for defects detection. The ability of gate layout improvement is based on the results of defects probabilities determination and identification of functional faults caused by these defects. The results are obtained by FIESTA-Extra software tool
Keywords :
design for testability; fault simulation; logic design; logic gates; FIESTA-Extra software tool; defect detection; defect probabilities determination; functional fault identification; gate layout improvement; industrial cell library; input test pattern; Automatic testing; Circuit faults; Circuit testing; Design for testability; Fault detection; Fault diagnosis; Pattern analysis; Software libraries; Software testing; Software tools;
Conference_Titel :
Microelectronics, 2006 25th International Conference on
Conference_Location :
Belgrade
Print_ISBN :
1-4244-0117-8
DOI :
10.1109/ICMEL.2006.1650980
