Gate Layout Improvement Aimed at Testability

In the presented paper the improvement of the layout of complex standard gates from the industrial cell library aimed at decreasing the probability of occurrence of undetectable faults is considered. Such improvement allows us to determine the defect coverage table correctly and as a result to estimate properly the optimal sequence of input test pattern for defects detection. The ability of gate layout improvement is based on the results of defects probabilities determination and identification of functional faults caused by these defects. The results are obtained by FIESTA-Extra software tool