• DocumentCode
    2207120
  • Title

    Reordering in Topology Decision Diagram Method for Symbolic Circuit Analysis

  • Author

    Djordjevic, S. ; Petkovic, P.M.

  • Author_Institution
    Dept. of Electron., Nis Univ.
  • fYear
    0
  • fDate
    0-0 0
  • Firstpage
    416
  • Lastpage
    419
  • Abstract
    This paper introduces reordering method in topology decision diagram (TDD) in order to enhance symbolic analysis method for RLC gm network function generation in nested form. The improvement is obtained in circuit function compression and the execution time. An example of n-th order ladder network illustrates the method
  • Keywords
    RLC circuits; decision diagrams; ladder networks; network analysis; network topology; RLC gm network function generation; ladder network; reordering method; symbolic analysis method; symbolic circuit analysis; topology decision diagram method; Admittance; Central Processing Unit; Circuit analysis; Circuit topology; Frequency; Intelligent networks; Network topology; Parameter extraction; Transfer functions; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronics, 2006 25th International Conference on
  • Conference_Location
    Belgrade
  • Print_ISBN
    1-4244-0117-8
  • Type

    conf

  • DOI
    10.1109/ICMEL.2006.1650989
  • Filename
    1650989
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2207120