Design considerations of the sub-50 nm self-aligned double gate MOSFET with a new channel doping profile

Presents a consideration to design a sub-50 nm self-aligned double gate MOSFET for fabrication by the theoretical analysis, 3D device simulation and process consideration. The scaling limits of gate length are decided by various elements which are analyzed. The optimization of the DG device structure parameters, such as thickness of Si film and spacer insulator is also illustrated. Meanwhile, we propose a new type of channel doping profile design, called SCD, whose advantages over other ways are discussed in detail. The balance between the volume inversion operation mode and the control of V_th in the DG MOSFET is achieved