High Speed Low Power CMOS Comparator for Pipeline ADCs

Author

Guermaz, M.B. ; Bouzerara, L. ; Slimane, A. ; Belaroussi, M.T. ; Lehouidj, B. ; Zirmi, R.

Author_Institution

Microelectron. & Nonotechnologies Div., Centre de Developpement des Technol. Avancees, Algiers

fYear

0

fDate

0-0 0

Firstpage

428

Lastpage

431

Abstract

This paper describes and analyzes a low power and high speed differential comparator. The designed comparator is intended to be implemented in a 10bit 20MHz pipeline analog-to-digital converter dedicated to RF WLAN applications. This comparator is based on the switched capacitor network using a two-phase nonoverlapping clock. The offset voltage of the designed comparator has been reduced by means of an active positive feedback. The analyses and simulation results which have been obtained using 0.8mum CMOS AMS process parameters, with a power supply voltage of 5V and an input common mode of 2-3V, show that this comparator exhibits a propagation delay of 17.3ns, a good accuracy and a low power consumption of about 0.8mW

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); low-power electronics; switched capacitor networks; 0.8 micron; 10 bit; 17.3 ns; 2 to 3 V; 20 MHz; 5 V; RF WLAN; high speed differential comparator; low power CMOS comparator; pipeline analog-to-digital converter; process parameters; switched capacitor network; two-phase nonoverlapping clock; Analog-digital conversion; Analytical models; CMOS process; Clocks; Feedback; Pipelines; Radio frequency; Switched capacitor networks; Voltage; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2006 25th International Conference on

Conference_Location

Belgrade

Print_ISBN

1-4244-0117-8

Type

conf

DOI

10.1109/ICMEL.2006.1650992

Filename

1650992