DocumentCode
2207262
Title
Effect of Cu damascene metallization on gate SiO2 plasma damage
Author
Bang, D.S. ; Hao, M.Y. ; Chen, S. ; Xiang, Q. ; Yeap, G. ; Lin, M.R.
Author_Institution
AMD, Sunnyvale, CA, USA
fYear
1998
fDate
4-5 Jun 1998
Firstpage
64
Lastpage
67
Abstract
The effect of using a Cu damascene process on plasma process-induced damage (PPID) is studied in relationship to future scaling rules. Wafers processed using a Cu damascene metallization scheme show little increase in gate leakage as antenna ratios are increased. This is in contrast to conventional Al wafers, which show a significant increase in gate leakage as the antenna ratio is increased. Applying this result to future technology generations shows that wafers produced with a Cu damascene process have the potential to exhibit significantly less gate leakage for future technology generations
Keywords
copper; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit yield; leakage currents; plasma materials processing; surface treatment; Al wafers; Cu damascene metallization; Cu damascene process; Cu-SiO2-Si; Si; antenna ratio; device scaling; gate SiO2 plasma damage; gate leakage; plasma process-induced damage; wafer processing; Antenna measurements; Current density; DC generators; Gate leakage; Leakage current; Metallization; Plasma applications; Plasma chemistry; Semiconductor diodes; Tunneling;
fLanguage
English
Publisher
ieee
Conference_Titel
Plasma Process-Induced Damage, 1998 3rd International Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
0-9651577-2-5
Type
conf
DOI
10.1109/PPID.1998.725575
Filename
725575
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