VLSI implementation of an extended Hamming neural network for non-binary pattern recognition

VLSI implementation of an extended Hamming neural network to classify non-binary input patterns is proposed. The Hamming extended network splits the input of a non-binary pattern into N binary input patterns, where N is the number of bits used for representing each pixel of the original input pattern. A Hamming neural network process each of the N binary input patterns in which the image is divided. A Winner-Take-All (WTA) structure selects the winner layer. The layer that has more winners decides the winner image. The VLSI Hamming network processes each binary pattern to measure the Hamming distance among the patterns under test and the reference. A CMOS WTA circuit identifies the winner pattern. An analog distance between patterns is proposed as an alternative method. The numerical difference between two pixels in the same relative position is computed and accumulated. The hole difference between every image and the reference pattern indicates how close an image is from the others. An architecture for this proposal is shown and compared with the extended neural network structure