Graded-Channel SOI nMOSFET Model Valid for Harmonic Distortion Evaluation

Author

de Souza, M. ; Pavanello, M.A. ; Cerdeira, A. ; Flandre, D.

Author_Institution

Lab. of Integrated Syst. of Polytech. Sch., Sao Paulo Univ.

fYear

0

fDate

0-0 0

Firstpage

476

Lastpage

479

Abstract

In this paper an evaluation of the harmonic distortion of graded-channel SOI nMOSFETs is performed. The analysis is carried out by comparing an analytical continuous model and experimental results. The total harmonic distortion, as well as the third and second order terms are used as figures of merit in this comparison. It is shown that GC SOI devices present better gain and linearity behavior than conventional devices and that these advantages are well described by the proposed analytical model. The results show that the proposed set of equations is able to describe the linearity behavior of GC devices, indicating its potential to be used in analog circuit simulation and design

Keywords

MOSFET; semiconductor device models; silicon-on-insulator; GC devices; conventional devices; figures of merit; gain behavior; graded channel SOI; harmonic distortion evaluation; linearity behavior; nMOSFET; set of equations; Analog circuits; Analytical models; Circuit simulation; Distortion measurement; Harmonic distortion; Linearity; MOSFET circuits; Performance evaluation; Postal services; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2006 25th International Conference on

Conference_Location

Belgrade

Print_ISBN

1-4244-0117-8

Type

conf

DOI

10.1109/ICMEL.2006.1651005

Filename

1651005