Title :
Asymmetries between PMOS and NMOS transistor in time-zero plasma charging damage
Author_Institution :
Philips Semicond. B.V, Crolles, France
Abstract :
Differences in time-zero plasma charging damage between PMOS and NMOS transistors are studied for an industrial 0.35 μm CMOS process. Asymmetries are reported in the sign and evolution of Vt-shift, gate leakage, and sensitivity to different plasma process steps
Keywords :
CMOS integrated circuits; MOSFET; integrated circuit testing; leakage currents; plasma materials processing; sensitivity; surface charging; surface treatment; 0.35 micron; CMOS process; NMOS transistor; PMOS transistor; Si; SiO2-Si; gate leakage; plasma process sensitivity; threshold voltage shift; time-zero plasma charging damage; transistor asymmetries; CMOS process; Diodes; Etching; Gate leakage; MOS devices; MOSFETs; Plasma applications; Production; Protection; Testing;
Conference_Titel :
Plasma Process-Induced Damage, 1998 3rd International Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
0-9651577-2-5
DOI :
10.1109/PPID.1998.725585
