Title :
Modeling and Simulation of Submicron MOSFETs with Alternative Gate Dielectrics for DRAM Cells
Author :
Konofaos, N. ; Alexiou, G. Ph
Author_Institution :
Dept. of Comput. Eng. & Informatics, Patras Univ.
Abstract :
In this study, we designed and simulated MOS devices having alternative gate dielectrics and examined their electrical behaviour as well as their effectiveness on the performance of a DRAM cell containing them. The devices under test had gate dielectrics of SrTiO3, (Ba1-xSrx)TiO3, TiO2, Ta2O5, Y2O3 and (Pb1 Lax)TiO3. Equivalent oxide thicknesses were derived between 0.95 and 4 nm. Among the candidate materials, SrTiO3 was the most promising when data retention is required, while Y2O3 depicted the best I-V behavior. An increased cell capacitance resulted to higher memory refreshing times, improving substantially the device reliability
Keywords :
DRAM chips; MOSFET; barium compounds; lanthanum compounds; lead compounds; semiconductor device models; semiconductor device reliability; strontium compounds; tantalum compounds; titanium compounds; yttrium compounds; (BaSr)TiO3; 0.95 nm; 4 nm; DRAM cells; I-V behavior; SrTiO3; Ta2O5; TiO2; Y2O3; alternative gate dielectrics; cell capacitance; data retention; device reliability; electrical behaviour; equivalent oxide thickness; memory refreshing times; submicron MOSFET; Circuit testing; Dielectric devices; Dielectric materials; High K dielectric materials; High-K gate dielectrics; Inorganic materials; Leakage current; MOS devices; MOSFETs; Random access memory;
Conference_Titel :
Microelectronics, 2006 25th International Conference on
Conference_Location :
Belgrade
Print_ISBN :
1-4244-0117-8
DOI :
10.1109/ICMEL.2006.1651007
