Title :
New memory-efficient hardware architecture of 2-D dual-mode lifting-based discrete wavelet transform for JPEG2000
Author :
Hsia, Chih-Hsien ; Chiang, Jen-Shiun
Author_Institution :
Dept. of Electr. Eng., Tamkang Univ., Taiwan
Abstract :
This work presents new algorithms and hardware architectures to improve the critical issues of the 2-D dual-mode (supporting 5/3 lossless and 9/7 lossy coding) lifting-based discrete wavelet transform (LDWT). The proposed 2-D dual-mode LDWT architecture has the advantages of low-transpose memory, low latency, and regular signal flow, which is suitable for VLSI implementation. The transpose memory requirement of the N Ã N 2-D 5/3 mode LDWT is 2N, and that of 2-D 9/7 mode LDWT is 4N. According to the comparison results, the proposed hardware architecture surpasses previous architectures in the aspects of lifting-based low-transpose memory size. It can be applied to real-time visual operations such as JPEG2000, MPEG-4 still texture object decoding, and wavelet-based scalable video coding.
Keywords :
discrete wavelet transforms; image coding; integrated memory circuits; video coding; 2D dual-mode lifting; JPEG2000; MPEG-4 still texture object decoding; discrete wavelet transform; low-transpose memory; memory-efficient hardware architecture; wavelet-based scalable video coding; Computer architecture; Delay; Discrete wavelet transforms; Electronic mail; Finite impulse response filter; Hardware; MPEG 4 Standard; Memory architecture; Two dimensional displays; Very large scale integration; 2-D 5/3 mode LDWT; 2-D 9/7 mode LDWT; interlaced read scan algorithm (IRSA); lifting-based discrete wavelet transform (LDWT); low-transpose memory;
Conference_Titel :
Communication Systems, 2008. ICCS 2008. 11th IEEE Singapore International Conference on
Conference_Location :
Guangzhou
Print_ISBN :
978-1-4244-2423-8
Electronic_ISBN :
978-1-4244-2424-5
DOI :
10.1109/ICCS.2008.4737288