Local Sealing of High Aspect Ratio Vias for Single Step Bottom-up Copper Electroplating of Through Wafer Interconnects

This paper presents a novel technology for copper electroplating in high aspect ratio silicon vias. The described approach is based on the bottom-up technology with the use of a new specifically designed electroplating holder for local sealing and filling of the vias. The technological steps are described and demonstrated for 20mum wide vias with an aspect ratio of 15. Moreover, a simplified simulation model is presented in order to explain the local sealing phenomenon and the subsequent electroplating.