DocumentCode
2208253
Title
A scalable systolic array architecture for the 2D discrete wavelet transform
Author
Chen, Jijun ; Bayoumi, Magdy A.
Author_Institution
Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
Volume
2
fYear
1995
fDate
13-16 Aug 1995
Abstract
Summary form only given, as follows. A systematic synthesis approach has been applied to the 2D discrete wavelet transform (DWT), and a scalable systolic array architecture has been derived based on the data dependence analysis and linear index space transformation. The architecture has regular topology, local routing, simple controller and high throughput rate, and it can be easily extended to different parameters of various levels, macroblocks and filters. The architecture has been implemented on Cadence Edge Framework
Keywords
network routing; network topology; systolic arrays; transforms; wavelet transforms; 2D discrete wavelet transform; Cadence Edge Framework; data dependence analysis; linear index space transformation; local routing; macroblocks; scalable systolic array architecture; throughput rate; topology; Computer architecture; Data analysis; Discrete wavelet transforms; Filters; Routing; Systolic arrays; Throughput; Topology; Wavelet analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on
Conference_Location
Rio de Janeiro
Print_ISBN
0-7803-2972-4
Type
conf
DOI
10.1109/MWSCAS.1995.510290
Filename
510290
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