The design and implementation of lattice codes using digital signal processing techniques

Addresses the design of lattice coding systems with the potential for both significant coding gain and very high speed operation, without impractical complexity. The conventional approach to the implementation of advanced modulation and coding schemes has been to employ general purpose programmable DSP chips. This limits the speed of operation to a few tens of kb/s at most, which has restricted the use of these schemes to applications such as voiceband modems. However, if the designer makes appropriate choices of lattice and algorithm it is possible to construct dedicated hardware, perhaps implemented in ASIC, capable of running at tens of hundreds of Mb/s. Two families of lattice which are suitable for hardware implementation are described. A suitable decoding algorithm is presented together with the resulting architecture