Optimization of an Application Specific Instruction Set Processor using Application Description Language

Application Specific Instruction Set Processor (ASIP) is becoming essential to convergent System on Chip (SoC) Design. Usually there are two approaches to design an ASIP. One of them is at Register Transfer Level (RTL) and another is at just higher level than RTL and is known as Electronic System Level (ESL). Application Description Languages (ADLs) are becoming popular recently because of its quick and optimal design convergence achievement capability during the design of ASIPs. This paper presents the implementation and optimization of an ASIP using an ADL known as Language for Instruction Set Architecture (LISA) and CoWare Processor Designer environment. The CoWare Processor Designer (PD) generates Software Development tools and synthesizable RTL for the processor. The generated RTL can be synthesized using Cadence Encounter.