DocumentCode
2208846
Title
A Compression Improvement Technique for Low-Power Scan Test Data
Author
Song, Jaehoon ; Yi, Hyunbean ; Hwang, Doochan ; Park, Sungju
Author_Institution
Dept. of Comput. Sci. & Eng., Hanyang Univ.
fYear
2006
fDate
14-17 Nov. 2006
Firstpage
1
Lastpage
4
Abstract
The huge test data volume, test time and power consumption are major problems in system-on-a-chip testing. To tackle those problems, we propose a new test data compression technique. Initially, don´t-cares in a pre-computed test cube set are assigned to reduce the test power consumption, and then, the fully specified low-power test data is transformed to improve compression efficiency by neighboring bitwise exclusive-or (NB-XOR) scheme. Finally, the transformed test set is compressed to reduce both the test equipment storage requirements and test application time
Keywords
data compression; integrated circuit testing; logic gates; low-power electronics; system-on-chip; test equipment; NB-XOR; low-power test data; neighboring bitwise exclusive-or scheme; power consumption; precomputed test cube set; system-on-chip testing; test data compression technique; Circuit testing; Computer science; Data engineering; Energy consumption; Filling; Power engineering and energy; System testing; System-on-a-chip; Test data compression; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON 2006. 2006 IEEE Region 10 Conference
Conference_Location
Hong Kong
Print_ISBN
1-4244-0548-3
Electronic_ISBN
1-4244-0549-1
Type
conf
DOI
10.1109/TENCON.2006.344040
Filename
4142590
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