DLX Processor Enhancement for AES Rijndael Crypto Algorithm

In this paper, we design a modified dlx processor to enhance its capability for Aes-Rijndael crypto algorithm processes. A component, named sub-byte, added to the dlx processor to handle sub-byte process, the most significant process in Rijndael crypto algorithm. We design new instruction class to access such component. The parameter used to measure the performance enhancement is processor speed in clock cycle time. The result verify our theoretical observation. We find the increasing processor speed to handle Rijndael crypto processes. This enhancement increases the dlx performance. Some software tools used to support several processes such as gccdlx-cross compiler c for dlx, winddlx-dlx processor simulator for window, and active HDL-compiler for VHDL