A high performance on-chip segmented bus architecture using dynamic bridge-by-pass technique

At present, VLSI technology makes it both feasible and economical to integrate a complex system on a single chip. With increase in number of components integrated to single System-on-Chip (SoC), there is corresponding increase in communication between them. This makes on-chip bus based communication a major challenge in current SoC technology. A segmented bus architecture shows potential for improving both speed and power related features of a bus-based system. Due to segmentation of the bus, parallel transactions can take place, thus increasing the performance of the bus. In order to reduce arbitration and communication delay in the existing segmented bus, new reconfigurable architectures which will completely avoid the complicated higher level arbitration over-head with a small modification in local arbiter is proposed in this paper. The bus architectures are modeled using VHDL and simulated using Xilinx ISE 9.2i. The simulation results show that the proposed architecture performs better than the existing segmented bus, in terms of operating frequency, communication delay and bandwidth. Hence the proposed architecture can be used for high speed real-time applications.