Mix/InvMixColumn decomposition and resource sharing in AES

In this paper, compact architectures for AES Mix Column and its inverse is presented to reduce the area cost in resulting AES implementation. In the hardware implementation of AES with direct mapping substitute byte optimization, MixColumn/Inverse MixColumn transformation demands the utilization of logic resources and then effects the critical path delay and resulting throughput. The proposed MixColumn/Inverse MixColumn design based on byte and bit-level decomposition leads to two types of architecture which demonstrates deeper resource sharing within byte and between bytes and rearrangement of output terms with respect to FPGA architecture in bit level resply. The proposed architectures have been investigated on a FPGA based implementation platform. Application of the proposed architectures resulted in reduction of reconfigurable logic area by 40% as compared to separate implementation of MixColumn and Inverse MixColumn reduction and also path delay by 9% resply. Experimental results show that our proposed architecture can reduce the area cost significantly and compared with other previous implementations reported so far.