A Statistical Jitter Tolerance Estimation Applied for Clock and Data Recovery Using Oversampling

In this article, an oversampling clock and data recovery unit (CDR) is introduced. Compared to the traditional PLL CDR, its intrinsic fast tracking performance makes it useful in burst model receiver. A jitter tolerance estimation based on ideal phase detection is introduced to assist systems analysis and performance parameters selection. The statistical simulation methodology enables much quicker verification of the bit error rate (BER) than direct BER measurement based on counting. The simulation results demonstrate the estimated jitter tolerance of the designed 155.52 Mb/s oversampling CDR with proper parameters well exceeds the jitter tolerance specified for STM-1 level of synchronous optical network (SDH)