Occurrence of Virtual Entanglement in Nano-CMOS logic

Using the theoretical framework of quantum mechanics we predict the possibility of occurrence of virtual entanglement in CMOS logic at nano-dimensions. Quantum mechanical properties such as superposition and entanglement are applied to CMOS logic and analysis is done using Dirac notation. The behavior of the n-type and p-type transistor during the computation phase is described. The parameter considered for analysis is state of the transistor and we obtain its behavior due to superposition and entanglement with other spatially separated transistors