Improvement on masked S-box hardware implementation

Masking in gate level could efficiently protect AES S-box out of power analysis attack. But there still exists a kind of attack, called glitch attack, to achieve the sensitive information from gate cell leakage. Some works had been done to resist against glitch attack, which carefully masked AND gate or used Wave Dynamic Differential Logic (WDDL) cell. In this paper, we propose an improved masked AND gate, in which the relationship between input masked values and masks is nonlinear. Usually, when converting S-box operations from GF(2⁸) to GF(((2²)²)²), all the necessary computations become XOR and AND operations. Therefore, to fully mask AES S-box is to substitute the unmasked XOR and AND operations with the proposed masked AND gate and protected XOR gate. Although the proposed masked AND gate take up one extra XOR gate than Trichina´s design and Baek´s design, it can resist against glitch attack without using specific gate cell, such as WDDL.