Key components of the fast reduced instruction set computer (FRISC) employing advanced bipolar differential logic and wafer scale multichip packaging

Author

Greub, H.J. ; McDonald, J.F. ; Creedon, T.

Author_Institution

Rensselaer Polytech. Inst., Troy, NY, USA

fYear

1988

fDate

12-13 Sep 1988

Firstpage

19

Lastpage

22

Abstract

Advanced bipolar circuits for a RISC operating at a 250 MHz instruction rate are presented. Specifically a 30×8 bit register file macro with 500-ps access time is presented and a clock skew compensation scheme based on digital delay lines is introduced that can significantly reduce clock skew in a wafer scale multichip package. The predicted performance of advanced bipolar memory macros, I/O circuitry, and differential logic circuit are very encouraging. Measurement on a fabricated divide by two circuits shows good agreement with SPICE simulations

Keywords

VLSI; bipolar integrated circuits; digital integrated circuits; packaging; reduced instruction set computing; 500 ps; I/O circuitry; SPICE simulations; access time; bipolar differential logic; clock skew compensation scheme; differential logic circuit; digital delay lines; divide by two circuits; fast reduced instruction set computer; instruction rate; memory macros; register file macro; wafer scale multichip packaging; Cache memory; Clocks; Computer aided instruction; Hardware; Logic; Packaging; Registers; Standards development; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar Circuits and Technology Meeting, 1988., Proceedings of the 1988

Conference_Location

Minneapolis, MN

Type

conf

DOI

10.1109/BIPOL.1988.51035

Filename

51035