The use of PROLOG for connectivity verification

The authors presents a connectivity verification program called VERCON implemented in PROLOG, that can handle both NMOS and CMOS designs. This system works by extracting the circuit hierarchy from the transistor level description. Verification is achieved when the top-level object is extracted and no redundant objects exist. Since no assumptions are made about the circuit topology, VERCON always works, something never achieved before. Also, problems due to symmetric circuits that plagued conventional approaches are handled automatically by VERCON