Design and implementation of interfacing two FPGAs

As FPGA performance and capabilities have increased substantially in recent years, FPGA-based designs are employed to implement complex functions and designs. The objective of our work is to design an interface between two FPGAs using I/O interface available inside FPGAs for the purpose of reliable communication. The two FPGAs will be connected via RS-232 port, to transfer data from one FPGA to another and vice versa. Our goal is to get a simple and reliable connection when two FPGAs communicate. The data information is created using Random Number Generator. We implemented our design using two Altera FPGA boards, implemented in Verilog™ language. Dynamic simulations were performed to verify the correctness of transmitted data. We had proposed a dice game as an application to show how two FPGAs can send and receive data to each other in full duplex direction. The two players generate a random number using Linear Feedback Shift Register (LFSR) algorithm then send their number to each other using RS-232 cross cable. Finally, the values are compared and whoever gets the larger number wins the game.