High performance CMOS device technologies in nano CMOS era

This paper reviews the results on the development of these carrier-transport-enhanced CMOS structures based on global novel substrate technologies and the combination of local techniques with them. Here, there are two new directions for the development of the global substrate technologies including new materials such as Ge and III-Vs. The other direction is the combination of any local formation technologies, allowing us to separately optimize the strain configuration and the channel materials for n-and p-MOSFETs for maximizing the CMOS performance.