High pressure deuterium annealing effect on nano- scale CMOS devices with different channel width

Author

Sung-Man Cho ; Jeong-Hyn Lee ; Chang, Mingchao ; Jo, M.-S. ; Hwang, H.-S. ; Lee, Jae-Kyung ; Jong-Ho Lee

Author_Institution

Sch. of Electron. & Electr. Eng. & Comput. Sci., KyungPook Nat. Univ., Daegu

Volume

1

fYear

2006

fDate

22-25 Oct. 2006

Firstpage

98

Lastpage

99

Abstract

High pressure deuterium annealing was applied to nano-scale CMOS devices which has Plasma Nitride Oxidation (PNO) gate oxide. The annealing effect was characterized in terms of different sizes, charge pumping, hot carrier and NBTI stress, and /f noise for the first time. The characteristics of NMOS were improved by the annealing. But PMOS has only improved NBTI characteristic. Devices with narrow channel width shown more significant effect than wide channel devices.

Keywords

CMOS integrated circuits; annealing; nanotechnology; NBTI stress; PNO; charge pumping; different channel width; high pressure deuterium annealing effect; nanoscale CMOS devices; plasma nitride oxidation gate oxide; Annealing; Charge pumps; Deuterium; Hot carriers; Nanoscale devices; Niobium compounds; Oxidation; Plasma devices; Plasma properties; Titanium compounds; 1/f noise; Charge pumping; High Pressure Deuterium Annealing; Hot carreir stress; NBTI; Nano-scale CMOS;

fLanguage

English

Publisher

ieee

Conference_Titel

Nanotechnology Materials and Devices Conference, 2006. NMDC 2006. IEEE

Conference_Location

Gyeongju

Print_ISBN

978-1-4244-0540-4

Electronic_ISBN

978-1-4244-0541-1

Type

conf

DOI

10.1109/NMDC.2006.4388705

Filename

4388705