Design of a reconfigurable parallel convolver

This paper introduces a parallel architecture for a linear and parallel convoler. The proposed architecture is a reconfigurable design for different parallel step size, S, and different data formats. In each clock cycle, S samples of input sequence are entered into the parallel convolver and S outputs are generated, simultaneously. Since the design is reconfigurable, one can reach to any needed speed, by adjusting the parallel step size, S. It is needed to mention that with increasing the parallel step size, S, the speed of the circuit increases more rapidly than its area. The proposed design also has the flexibility to be adjusted for different applications, via altering its parameters. In order to validate the functionality of the proposed architecture, a computer simulation is developed for the designed convolver. Also, in order to evaluate the performance of the architecture in a hardware platform, the proposed parallel convolver has been implemented on an FPGA device; and it has been tested for different parallel step sizes. The performance of our proposed architecture is compared to other designs, in terms of time (T), area-time product (AT), and area-time-square product (AT²). This comparison shows the superiority of our design to the others.