Low complexity digital clock recovery algorithm for implementation in software-defined radios

Software-defined radios (SDR) require robust synchronization algorithms which are suitable for implementation on generic programmable platforms. In this paper, we propose and study a low-complexity digital clock recovery scheme for implementation on programmable digital signal processing (DSP) or field-programmable gate-array (FPGA) platforms. Performance is established in terms of mean-square timing error and the required computational complexity. It is shown that the proposed algorithm achieves a superior performance as compared with the existing algorithms for a wide range of operating parameters.